Method and apparatus for designing a PLL

ABSTRACT

A method and apparatus for designing a PLL enables initial component characteristics and design specifications of the PLL to be specified. Time constants for a loop filter that would be required to create a PLL having the desired design specifications and component characteristics are then computed. The performance or behavior characteristics of the PLL may then be computed for the PLL given the time constants and the initial set of components, to determine whether the performance of the PLL would be considered satisfactory. For example, PLL design software may determine whether a PLL would be sufficiently stable if it was to be created using the particular selected components given the required design specifications. Where the PLL does not meet particular behavior characteristics, the PLL design software may provide guidance as to what component characteristics would improve performance of the PLL. Designed PLLs may be used for timestamp based clock synchronization.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.60/674,231, filed Apr. 23, 2005 entitled A Clock SynchronizationTechnique With Improved Clock Stability, and is also related to U.S.patent application Ser. No. 10/076,415, filed Apr. 19, 2002 entitledTechnique for Synchronizing Clocks in a Network, the content of each ofwhich is hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to communication networks and, moreparticularly, to a method and apparatus for designing a Phase-LockedLoop (PLL).

2. Description of the Related Art

Data communication networks may include various computers, servers,routers, switches, hubs, proxies, and other devices coupled to andconfigured to pass data to one another. These devices will be referredto herein as “network elements.” Data is communicated through the datacommunication network by passing data over an established circuit or bypacketizing the data and routing the data packets between a series ofnetwork elements over the network.

There are two basic types of networks—Time Division Multiplexed (TDM)networks and packet networks. These two networks differ in how data aretransmitted on the physical medium. In a TDM network, data belonging todifferent users are assigned different timeslots, otherwise called“circuits’ or “channels” in a given time interval otherwise called a“frame”. A user can only transmit in its assigned time slot in a framethat continuously repeats itself. The clocking or timing signal thatgenerates the frames and timeslots on the physical medium has to be veryaccurate for transmissions to be successful. Thus, in a TDM network, thenetwork elements rely on accurate timing to determine which user databelong to which circuit, whereas in a packet network the packets areindividually addressed in a manner that is able to be understood by thenetwork elements. Since TDM networks rely on accurate timing to divideframes between multiple logical channels in existence on the samephysical wire/optical fiber, timing requirements of TDM networks aregenerally relatively stringent. In a packet network, by contrast, timingis less important since each packet of data is self-contained and isable to specify to the network element its size and other associatedparameters. Since timing is not as stringent on a packet network, thenetwork elements on a packet network are generally not synchronized to acommon timing source. Hence, packet networks are generally referred toas asynchronous networks.

TDM networks are synchronous in nature. Consequently, the equipmentconnected to a TDM network has to be synchronized to it in some manner.In a TDM network, a timing distribution network typically will link theTDM nodes to provide a synchronization signal that is traceable to aPrimary Reference Source (PRS). The network synchronization signal isderived from the PRS and distributed through a hierarchy of networknodes with lesser stratum clocks. An alternative timing solution is tomaintain a distributed PRS architecture, where for example, each TDMnode is timed from an accurate timing source, such as a PRS/Stratum 1clock, Global Positioning System (GPS) based clock, or a standaloneaccurate clock (e.g., H Maser, Cesium, Rubidium, etc.). The particulartiming requirements on a service interface depend on the services (T1,E1, T3, E3, etc.) carried over the network, which are typicallyspecified in a standard promulgated for that particular service type.

As packet technology has increased in reliability and sophistication,the cost of deploying packet-based networks such as Ethernet networksand Internet Protocol (IP) networks has dropped to the point where it isoften cheaper to deploy a packet network than to deploy a TDM network.To take advantage of the lower costs of packet network technology,service providers have sought to implement packet-based core networksintermediate existing TDM networks. To allow a packet network to carryTDM traffic, the packet network must essentially behave as a transparent“link” in the end-to-end connection. The transparent inclusion of apacket network in an end-to-end path of a connection that carriescircuit-switched time sensitive traffic is commonly referred to as“circuit emulation” on the packet network.

The non-synchronous nature of the packet network and the packetizing anddepacketizing processes used to format the data for transmission overthe packet network all contribute to increased delay and delayvariations in the transmission of packets, which makes transfers ofsynchronization between the TDM networks on either side of the packetcore difficult. Additionally, while packet networks are able to carrytraffic between the end TDM networks, they do not naturally carryaccurate clock information due to their asynchronous nature. Thus, toenable TDM traffic to be carried over a packet network, it is necessaryto have the end systems directly exchange clock information, so that thedata ports on the network elements can be synchronized and to allow thedifferent networks to be synchronized.

To overcome the inherent non-synchronous nature of a packet network, anetwork element or a downstream terminal mode may use an adaptive timingtechnique to reconstruct the timing signal of the upstream TDM terminal.For example, where there are no reference clocks traceable to a PRS, areceiving TDM terminal node has to use an adaptive timing technique toreconstruct the timing signal of the transmitting TDM terminal. In anadaptive clocking technique, the TDM receiver derives an estimate of thetransmitter clock from the received data stream. This is commonly doneusing a phase-locked loop (PLL) that slaves the receiver clock to atransmitter clock. The slave PLL is able to process transmitted clocksamples encoded within the data stream, or process data arrivalpatterns, to generate timing signals for the receiver. The purpose ofthe slave PLL is to estimate and compensate for the frequency driftoccurring between the oscillators of the transmitter clock and thereceiver clock.

Several adaptive timing techniques have been developed, includingextracting clock information from arrival patterns over the network,observing the rate at which the buffers are being filled, and usingencoded timing signals transmitted from the upstream terminal to thedownstream terminal across the packet network. One example of the use ofencoded timing signals (timestamps) is described in U.S. patentapplication Ser. No. 10/076,415, entitled “Technique for SynchronizingClocks in a Network”, the content of which is hereby incorporated byreference.

In this previous application, a PLL was developed that included alow-pass filter, however the PLL in that solution was not developedquantitatively, but rather was developed by experimental trials. Toincrease the performance of the PLL, such as to increase the jitterattenuation, a higher order PLL may be used at the slave clock. However,as the order of the PLL increases, such as where second and third orderPLLs are to be used to increase the jitter attenuation performance ofthe PLL, designing a PLL by experimental trials becomes increasinglydifficult and cumbersome. Accordingly, it would be advantageous toprovide a software program configured to assist in the design of a PLLgiven a set of performance specifications, (e.g., system damping factor,etc.) and component characteristics (such as VCO characteristic curve,digital-to-analog (DAC) word size (in bits), etc.).

SUMMARY OF THE INVENTION

The present invention overcomes these and other drawbacks by providing amethod and apparatus for designing a timestamp-based phase-locked loopfor clock synchronization in a packet network. According to anembodiment of the invention, PLL design software is provided that isconfigured to enable initial component characteristics to be specified,enable design specifications of the PLL to be specified, and to computethe time constants for a loop filter that would be required to enable aPLL to meet the design specifications given the componentcharacteristics. The performance or behavior characteristics of the PLLmay then be computed for the PLL given the time constants and theinitial set of components to determine whether the performance of thePLL would be considered satisfactory. For example, the PLL designsoftware may determine whether the PLL would be sufficiently stable ifcreated using the particular selected components given the requireddesign specifications. Where the PLL does not meet particular behaviorcharacteristics, the PLL design software may provide guidance as to whatcomponent characteristics would improve performance of the PLL. Once thePLL is designed, the PLL design may be implemented in hardware to form aPLL. The PLL design software is particularly useful in designingtimestamp-based PLLs for clock synchronization in a packet network.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present invention are pointed out with particularity inthe appended claims. The present invention is illustrated by way ofexample in the following drawings in which like references indicatesimilar elements. The following drawings disclose various embodiments ofthe present invention for purposes of illustration only and are notintended to limit the scope of the invention. For purposes of clarity,not every component may be labeled in every figure. In the figures:

FIG. 1 is a functional block diagram of an example communication networkover which clock synchronization may take place using a PLL designedusing the PLL design software according to an embodiment of theinvention;

FIG. 2 is a functional block diagram of a PLL configured to usetimestamps;

FIG. 3 is a graph illustrating the PLL input and output;

FIG. 4 is a graph illustrating the power spectrum of an output signal ofa PLL;

FIG. 5 is a flow chart illustrating a process of synchronizing clocks ona network using timestamps;

FIG. 6 is a functional block diagram of a PLL implemented using avoltage controlled oscillator;

FIG. 7 is a graph illustrating the behavior of a phase detector in thePLL of FIG. 6;

FIG. 8 is a graph illustrating the phase detector signals in both bitsand radians;

FIG. 9 is a graph illustrating the phase detector characteristics overtime;

FIG. 10 is a graph illustrating an ideal voltage controlled oscillatorcharacteristic curve;

FIG. 11 is a functional block diagram illustrating a closed loop controlmodel of the PLL of FIG. 6;

FIGS. 12 a and 12 b are magnitude and phase plots, respectively, of thefrequency response of the 2^(nd) and 3^(rd) order PLLs that may bedesigned using the PLL design software according to an embodiment of theinvention;

FIG. 13 is a functional block diagram of a PLL with error-DAC/VCOmapping functions shown in the discrete time domain; and

FIGS. 14 a and 14 b are flow charts of a dynamic mapping functionprocess using, respectively, samples in non-overlapping windows andsamples in overlapping windows;

FIG. 15 is a flowchart illustrating a process of designing a PLLaccording to an embodiment of the invention; and

FIG. 16 is a functional block diagram of a computer system configured torun PLL design software configured according to an embodiment of theinvention.

DETAILED DESCRIPTION

The following detailed description sets forth numerous specific detailsto provide a thorough understanding of the invention. However, thoseskilled in the art will appreciate that the invention may be practicedwithout these specific details. In other instances, well-known methods,procedures, components, protocols, algorithms, and circuits have notbeen described in detail so as not to obscure the invention.

FIG. 1 illustrates an example network 10 in which clock information 12is carried across a packet network 14 from a master clock 16 to one ormore slave clocks 18. As shown in FIG. 1, synchronization of the masterand slave clocks is achieved over a packet (non TDM) portion of thenetwork 14 by transmitting packets 12 containing clock state informationfrom the master clock 16 to the slave clocks 18.

When timestamps are used for clock synchronization, a transmitter 16periodically sends explicit time indications, or timestamps, to areceiver 18 to enable the receiver to synchronize its local clock 22 tothe transmitter's clock 20. Although FIG. 1 only shows a singlereceiver, the timestamp synchronization strategy also allows multiplereceivers, for example in a broadcast or point-to-multipointcommunication scenario, to synchronize their clocks to the transmitter.

The transmitter clock includes an oscillator 30 and a pulse counter 32.The oscillator issues periodic pulses 34 that form the input to thepulse (timestamp) counter 32. The output of the counter 32 representsthe transmitter clock signal 36, and is incremented by a fixed amount ateach pulse. Samples of the transmitter clock signal are communicated tothe receiver 18 as timestamps.

The receiver clock 22 is formed as a Phase-Locked Loop (PLL) which usesthe timestamps 12 (which form the PLL reference signal) to lock onto thetransmitter clock 20. The PLL 22 has four main components: a phasedetector 40, a loop filter 42, a local oscillator such as a VoltageControlled Oscillator (VCO) or Current Controlled Oscillator (CCO) 44,and a timestamp counter 46. Although an embodiment of the invention willbe described in connection with designing a PLL that uses a VCO, theinvention is not limited in this manner as a CCO may be used in thedesign process as well. The phase detector 40 computes an error signal50 as the difference between a reference signal 54 and the output signalof the PLL 56. The error signal 50 is passed on to the loop filter 42which is responsible for eliminating possible jitter and noise in theinput signal. The local oscillator such as the VCO 44, which typicallyhas a center frequency, oscillates at a frequency which is determined bythe output signal of the loop filter.

FIG. 2 shows an example of a PLL configured to use a timestamps as aninput. In this PLL, T(n) will be used to denote the time base (e.g., inclock ticks) of the transmitter and R(n) will be used to denote the timebase of the receiver. These two functions correspond to the timestampsof the two clocks at discrete time instants n, n=0,1,2, . . . . Whentimestamps are transmitted over the packet network, they will arrive atthe receiver with variable delay. If d(n) and d(n−1) denote the delayexperienced by the nth and (n−1)th timestamp at the receiver,respectively, then the delay variation induced by the network is givenas j(n)=d(n)−d(n−1). The timestamp difference between the nth and(n−1)th generated timestamp at the transmitter is defined asΔT(n)=T(n)−T(n−1). At the receiver, the timestamp difference between thenth and n−1th timestamp arrivals as measured by the receiver clock isdefined as ΔR(n)=R(n)−R(n−1). Note that the timestamp differencemeasured by the receiver includes the delay variation experiencedbetween the two arrivals, that is, ΔR(n)=ΔT(n)+j(n). If there is zerodelay variation and the transmitter and receiver have the samefrequency, then ΔR(n)=ΔT(n).

Now the clock recovery problem may be formulated as follows: Whilefiltering out delay variation, the receiver clock frequency {circumflexover (f)}_(s)=1/{circumflex over (τ)}_(s) 56 is controlled so that thereceiver clock measurements ΔR(n) 60 are equal to the transmitter clocktimestamp differences ΔT(n). The difference between ΔT(n) and ΔR(n)forms an error signal, e(n)=ΔT(n)−ΔR(n) (50). This error signal 50 isfiltered by the loop filter 42 of a PLL whose output then controls thefrequency {circumflex over (f)}_(s)=1/{circumflex over (τ)}_(s) of theVCO 45 of the receiver clock as shown in FIG. 2. The function of the PLLis to control the receiver clock frequency {circumflex over (f)}_(s)such that the error e goes to zero at which point the receiver frequencyequals the transmitter frequency f_(s). The loop filter 42, in this PLL,is a simple low-pass filter.

The PLL at the receiver therefore takes ΔT(n) as its reference input andgenerates ΔR(n) as its output (i.e., the controlled process). The twoprocess variables ΔT(n) and ΔR(n) are illustrated in FIG. 3.

To create a PLL, it is necessary to select components that will providethe PLL with the desired characteristics and responsiveness. One way todo this is to select the components by iterative experimentation. Forexample, components may be selected, a loop filter designed, and the PLLmay be tested to determine its responsiveness and stabilitycharacteristics. While this may be possible for lower order PLLs, suchas first order PLLs, successfully designing a second or third order PLLmay take significant experience and skill on the part of the designer,since it is not always clear how changing one of the components willaffect the overall behavior of the PLL. To improve on this manualprocess, according to an embodiment of the invention, PLL designsoftware is provided that is configured to automate the process ofdesigning the PLL, given a set of performance specifications andcomponent characteristics.

To understand how the PLL design software is configured to perform PLLdesign, it is first necessary to understand how the components of a PLLinteroperate with each other and to understand the manner in which thePLL operates.

To explain why a suitably chosen low-pass filter is required as the loopfilter, consider the expression ΔR(n)=ΔT(n)+j(n), wherej(n)=d(n)−d(n−1), as developed earlier. The network delays d(n) areassumed to be independent identically distributed (i.i.d) randomvariables with mean μ_(d) and variance σ_(d) ². The delay variationprocess j(n) has a mean of μ_(j)=E[j(n)]=0 and its autocorrelationR_(j)(k) is given by $\begin{matrix}{{R_{j}(k)} = {{E\left\lbrack {{j\left( {n + k} \right)}{j(n)}} \right\rbrack}\quad = {{{E\left\lbrack {{d\left( {n + k} \right)}{d(n)}} \right\rbrack} - {E\left\lbrack {{d\left( {n + k} \right)}{d\left( {n - 1} \right)}} \right\rbrack} - \quad{E\left\lbrack {{d\left( {n + k - 1} \right)}{d(n)}} \right\rbrack} + {E\left\lbrack {{d\left( {n + k - 1} \right)}{d\left( {n - 1} \right)}} \right\rbrack}}\quad = {{{2{R_{d}(k)}} - {R_{d}\left( {k + 1} \right)} - {R_{d}\left( {k - 1} \right)}}\quad = \left\{ \begin{matrix}{{2\left( {\sigma_{d}^{2} + \mu_{d}^{2}} \right)},} & {k = 0} \\{{- \left( {\sigma_{d}^{2} + \mu_{d}^{2}} \right)},} & {k = {\pm 1}} \\{0,} & {otherwise}\end{matrix} \right.}}}} & (1)\end{matrix}$The power spectral density S_(j)(f) of j(n) is given by $\begin{matrix}\begin{matrix}{{S_{j}(f)} = {\sum\limits_{k = {- 1}}^{1}{{R_{j}(k)}{\mathbb{e}}^{{- {\mathbb{i}2\pi}}\quad{fk}}}}} \\{= {\eta\left( {2 - {\mathbb{e}}^{{\mathbb{i}}\quad 2\pi\quad f} - {\mathbb{e}}^{{- {\mathbb{i}}}\quad 2\quad\pi\quad f}} \right)}} \\{{= {2\eta\left( {1 - {\cos\quad 2\pi\quad f}} \right)}},}\end{matrix} & (2)\end{matrix}$where η=σ_(d) ²+μ_(d) ². Without loss of generality, it will be assumedthat the transmitter generates timestamps with a constant interval of ΔT(i.e., ΔT is constant for all n). Then the z-transform and the powerspectral density of ΔR(n) are given byΔR(z)=ΔT+j(z)   (3)S _(ΔR)(f)=ΔT ²δ(f)+S _(j)(f)=ΔT ²δ(f)+2η(1−cos 2πfT _(s)),   (4)note that these equations have used the fact that the Fourier transformof a constant is a delta function and T_(s) is the sampling, which inthis case is equal to the inter-timestamp period ΔT. The power spectraldensity S_(ΔR)(f), which is shown in FIG. 4, contains a dc componentequal to the timestamp generation interval and the spectrum of the delayvariation process.

Because the delay variation and noise contribution at dc is zero,theoretically, by using an appropriate low-pass filter to remove thedelay variation and noise in the high-frequency region, the period(frequency) of timestamp generation can be estimated to an arbitrarydegree of accuracy. As set forth in greater detail below, a suitable lowpass filter may be designed given certain performance specifications ofthe PLL according to an embodiment of the invention.

FIG. 5 illustrates a process used by the PLL to control the VCO toestimate the transmitter clock. The measurement/computational instantsin the flowchart occur at the timestamp arrival instants at thereceiver. Initially, the PLL at the receiver sets the initial digitalloop filter parameters (100) and initializes variables (102). The PLLthen waits for the first timestamp to arrive (104).

When the first timestamp arrives it is loaded into the counter. Fromthis point onwards, the PLL starts to operate in a closed-loop fashion.Each time the Kth (K≧1, where K is a downsampling parameter) timestamparrives (106) (i.e., at sampling instant n=1,2,3, . . . ), thedifference ΔT(n) between this value T(n) and the value at the previoussampling instant T(n−1) is determined. The difference ΔT(n) is thencompared to the timestamp inter-arrival time ΔR(n)=R(n)−R(n−1) measuredby the receiver PLL counter (108) to give an error term e(n)=ΔT(n)−ΔR(n)(110). This error term is sent to the loop filter (112) whose outputcontrols the frequency of the VCO. The output of the VCO in turnprovides the clock frequency of the receiver and also drives thecounter. After a while the error term is expected to converge to zerowhich means the PLL has been locked to the incoming time base, i.e.,time base of the transmitter.

FIG. 6 shows the basic components of a PLL architecture with a VCO. Thephase detector 40 compares an arriving transmitter timestamp differenceagainst the timestamp difference of the receiver clock. The output ofthe phase detector, called the error, is a measure of the frequencydifference between the two clocks. The error is then filtered by theloop filter 42. The signal u is converted to an analog signal using adigital-to-analog converter (DAC) 62. A Zero-Order Hold (ZOH) circuit(implemented separately or as part of the DAC) maintains the samevoltage throughout the sample period. The analog voltage is thenamplified by an amplifier 64 before being applied to the VCO. The mainfunction of the amplifier, in this example, is to scale the inputvoltage to the VCO within the acceptable VCO voltage range. The controlvoltage on the VCO changes the frequency in a direction that reduces thedifference between the input frequency and the local oscillator. Notethat the minimum frequency resolution of the VCO is dependent on theresolution (quantization step size) of the DAC. Higher resolution of theDAC provides finer frequency control of the VCO. In the synchronized(often called the locked) state, the error between the localoscillator's output signal and the transmitter's signal is zero orremains a very small random quantity.

In some PLL designs, a current-controlled oscillator (CCO) is usedinstead of the VCO. In this case, the output signal of the DAC is acontrolled current source rather than a voltage source. However, theoperating principle remains the same.

As discussed above in connection with the general description of a PLL,a PLL is a feedback control system. Assuming that the phase errorθ_(e)(θ_(e)(t)=θ_(ref)(t)−θ_(VCO)(t) is the difference between the VCOclock phase θ_(VCO)(t) and the reference clock phase θ_(ref)(t)) iswithin a limited range, this feedback control system can be furthersimplified as linear feedback control system. This assumption isreasonable for most applications since a real PLL has a bounded andlimited locking range (expressed in parts-per-million, ppm, of thenominal operating frequency), outside of which locking cannot beguaranteed. The small signal linear analysis for the PLL is thereforeuseful for studying steady-state equilibrium behavior and stabilityproperties under these same conditions. To enable a PLL to be designedusing an automated process such as a computer program, it is firstnecessary to develop control models for the phase detector, digital toanalog converter, voltage controlled oscillator, and given some generalstructure of the loop filter, the PLL as a whole. The analysis willfurther provide design procedures for determining the parameters of theloop filter that will meet certain pre-specified design and performancerequirements. Some design steps are provided so that those with limitedknowledge of control systems can still determine the parameters of thePLL given only the performance specifications.

The behavior of the phase detector is illustrated in FIG. 7. Assume thatthe timestamp generation period is constant, that is, ΔT(n)=ΔT and thatthere is no delay variation in the system. The phase detector willdetermine a phase error approximately every ΔT(n) (bit) interval. In thePLL, essentially, the input frequencies f_(s) and {circumflex over(f)}_(s) are essentially divided down to lower frequencies which wedenote as f_(ΔT)=f_(s)/ΔT and f_(ΔR)={circumflex over (f)}_(s)/ΔR,respectively, before being passed to the phase detector. In this case,measurements and control are done every ΔT interval, thus, ΔT tick isequivalent to 2π radians. FIG. 8 shows this relationship. Note that in aPLL, if measurements and control are done on a bit-by-bit basis, anerror of 1 clock tick is equivalent to 2π radians. This is alsoanalogous to the case of observing an error of 1 bit off a threshold inan elastic-buffer type PLL, where errors are measured in bits orfractions of a bit around a buffer threshold.

Therefore, given an error e(t) in bits and a phase error θ_(e)(t) inradians, the following may be used to express the bit error-phase errorrelationship: $\begin{matrix}{{{\frac{e(t)}{\Delta\quad T} = \frac{\theta_{e}(t)}{2\pi}},{or}}{{e(t)} = {\frac{\Delta\quad T}{2\pi} \cdot {{\theta_{e}(t)}.}}}} & (5)\end{matrix}$With this, it is possible to write the phase detector gain as$\begin{matrix}{K_{PD} = {\frac{\Delta\quad T}{2\quad\pi}.}} & (6)\end{matrix}$The phase detector characteristic curve is shown in FIG. 9. As shown inFIG. 9, the phase detector gain is equal to the slope of itscharacteristic curve.

It is reasonable to assume that the PLL is operating in thecontinuous-time domain. In this domain, the phase detector measures thephase difference θ_(e)(t)=θ_(ref)(t)−θ_(VCO)(t) between the VCO clockphase θ_(VCO)(t) and the reference clock phase θ_(ref)(t), and developsan output e(t) that is proportional to this phase-frequency differenceθ_(e)(t). The ranges of θ_(e)(t) are −π<θ_(e)(n)<π. This operation canbe expressed ase(t)=K _(PD)·θ_(e)(t)   (7)The error signal output e(t) is then passed to the loop filter G_(LF)(s)to be processed into the filtered error {tilde over (e)}(t). Thetransfer function of the phase detector may then be given as:$\begin{matrix}{{{G_{PD}(s)} = {\frac{E(s)}{\Theta_{e}(s)} = {K_{PD} = \frac{\Delta\quad T}{2\quad\pi}}}},} & (8)\end{matrix}$where E(s) and Θ_(e)(s) are the Laplace transforms of e(t) and θ_(e)(t),respectively.

The Digital to Analog Converter (DAC) and the Voltage ControlledOscillator (VCO) determine the accuracy of the PLL. To model thesecomponents, the following variables are defined:

-   -   u(t)=DAC output voltage (in volts)    -   ΔV_(DAC)=DAC output voltage range (which is also the VCO input        voltage range)    -   DAC_(res)=DAC resolution=2^(L),where L is the DAC register        length in bits, e.g., L=12 bits        Thus, given a filtered error value {tilde over (e)}(t), the DAC        produces a voltage according to the following formula:        $\begin{matrix}        {{u(t)} = {\frac{\Delta\quad V_{DAC}}{{DAC}_{res}} \cdot {{\overset{\sim}{e}(t)}.}}} & (9)        \end{matrix}$        The above equation means that the VCO input voltage range        ΔV_(DAC) is quantized into DAC_(res) values. Assuming in this        equation that the error value {tilde over (e)}(t) is expressed        as an integer number 0 to DAC_(res)−1, the Laplace transform of        the expression is given as $\begin{matrix}        {{{U(s)} = {\frac{\Delta\quad V_{DAC}}{{DAC}_{res}} \cdot {\overset{\sim}{E}(s)}}},} & (10)        \end{matrix}$        which yields the DAC transfer function: $\begin{matrix}        {{{G_{DAC}(s)} = {\frac{U(s)}{\overset{\sim}{E}(s)} = \frac{\Delta\quad V_{DAC}}{{DAC}_{res}}}},} & (11)        \end{matrix}$        where {tilde over (E)}(s) and U(s) are the Laplace transforms of        {tilde over (e)}(t) and u(t), respectively.

To obtain a model for the VCO, it will be assumed that the DAC outputvoltage u(t) does not need any amplification, thus A=1. The VCOoscillates at an angular frequency ω_(VCO)(t) which is determined by theDAC output voltage u(t). The angular frequency of the VCO ω_(VCO)(t) isgiven byω_(VCO)(t)=ω_(o) +K _(VCO) u(t),   (12)where ω_(o)=2πf_(o) is the center angular frequency of the VCO(expressed in rad/sec), f_(o) is the center frequency in Hertz, andK_(VCO) is the VCO gain (in rad/sec-V). The deviation of the VCO fromits center frequency is Δω_(VCO)(t)=K_(VCO)u(t).

By definition the VCO phase θ_(VCO) is given by the integral over thefrequency variation Δω=ω_(VCO)(t)−ω_(o), that is, $\begin{matrix}{{\theta_{VCO}(t)} = {{\int_{0}^{t}{\Delta\quad{\omega(x)}{\mathbb{d}x}}} = {K_{VCO}{\int_{0}^{t}{{u(x)}{{\mathbb{d}x}.}}}}}} & (13)\end{matrix}$Denoting Θ_(VCO)(s) as the Laplace transform of θ_(VCO)(t), the Laplacetransform of the above expression is given by $\begin{matrix}{{{\Theta_{VCO}(s)} = {\frac{K_{VCO}}{s}{U(s)}}},} & (14)\end{matrix}$from which the transfer function of the VCO may be obtained as:$\begin{matrix}{{G_{VCO}(s)} = {\frac{\Theta_{VCO}(s)}{U(s)} = {\frac{K_{VCO}}{s}.}}} & (15)\end{matrix}$This expression shows that the VCO represents a pure integrator forphase signals.

The operation of the PLL is complicated by the fact that it has to trackthe reference clock and simultaneously reject short term variations.From a functional point of view, the PLL should be able to operate toprovide a very stable clock when synchronized to the external network,and should also be able to provide a stable clock when synchronizationis lost (holdover mode). In holdover mode the feedback loop is open, andthe circuit does not behave as a PLL.

The gain of the VCO can be computed from the VCO data sheet, which isgenerally obtainable from the VCO supplier. The first requirement is thedetermination of the supply voltage(s) of the VCO (this can bedetermined from the data sheet). For example, the VCO circuit may beable to be powered from a unipolar +5V supply. Let the VCO supplyvoltage be denoted by U_(supply). The VCO control signal u(t) is usuallylimited to a range which is smaller than the supply voltage U_(supply).Let u_(min) and u_(max) be the minimum and maximum value allowed foru(t), respectively. With these, the VCO transfer characteristic curvemay be described as shown in FIG. 10.

The VCO is required to generate the frequency ω_(VCO) _(—) _(min) whenu(t)=u_(min), and the frequency ω_(VCO) _(—) _(max) when u=u_(max). Nowthe angular frequency is determined at u=U_(supply)/2 which correspondsto a frequency ω_(o) that is considered as the center frequency of thePLL (irrespective of the fact that the center frequency could be varying(e.g., due to temperature effects, aging)). From FIG. 10 the VCO gaincan be calculated as $\begin{matrix}{K_{VCO} = {\frac{\omega_{VCO\_ max} - \omega_{VCO\_ min}}{u_{\max} - u_{\min}} = {\frac{{\Delta\omega}_{VCO}}{\Delta\quad V_{DAC}}.}}} & (16)\end{matrix}$The frequency axis of the VCO characteristics is sometimes expressed inHertz instead of radians per second. In this case, the gain is obtainedas $\begin{matrix}{K_{VCO} = {\frac{2{\pi\left( {f_{VCO\_ max} - f_{VCO\_ min}} \right)}}{u_{\max} - u_{\min}} = {\frac{2{\pi \cdot \Delta}\quad f_{VCO}}{\Delta\quad V_{DAC}}.}}} & (17)\end{matrix}$Furthermore, if the frequency axis is expressed in parts-per-million(ppm) of the VCO center frequency, the gain is calculated as$\begin{matrix}{{K_{VCO} = \frac{2{\pi \cdot f_{0} \cdot \Delta}\quad{ppm}}{\Delta\quad V_{DAC}}},} & (18)\end{matrix}$where f_(o) is the VCO center frequency and Δppm is the VCO outputfrequency range in ppm.

To model the PLL as a whole, denote Θ_(ref)(s) as the Laplace transformof θ_(ref)(t). The closed-loop control model of the PLL is shown in FIG.11. The order of the loop is equal to the number of perfect integratorswithin the loop structure. Since the VCO is modeled as a perfectintegrator, the loop is at least of order 1. If the loop filter alsocontains one perfect integrator, then the loop is of order 2.

The order of the loop can be shown to greatly influence the steady-stateperformance of the loop. The performance of the third-order PLL iscompared with the conventional second-order PLL (with a lag-lead filter)as shown in FIGS. 12 a and 12 b. As shown in FIGS. 12 a-12 b, anappropriately designed third-order PLL can exhibit much betterperformance than a second order A third order PLL may be more difficultto design than a second order PLL, however, where a trial and errorapproach is taken to PLL design.

Given the models described above for the DC, VCO, and DAC, the transferfunction for the PLL may be written as: $\begin{matrix}\begin{matrix}{{G_{PLL}(s)} = \frac{\Theta_{VCO}(s)}{\Theta_{ref}(s)}} \\{= \frac{{G_{PD}(s)}{G_{LF}(s)}{G_{DAC}(s)}{G_{VCO}(s)}}{1 + {{G_{PD}(s)}{G_{LF}(s)}{G_{DAC}(s)}{G_{VCO}(s)}}}} \\{= \frac{K_{gain}{G_{LF}(s)}}{s + {K_{gain}{G_{LF}(s)}}}}\end{matrix} & (19)\end{matrix}$where the forward gain K_(gain) is given as $\begin{matrix}\begin{matrix}{K_{gain} = {K_{PD}K_{DAC}K_{VCO}}} \\{{= \frac{\Delta\quad{T \cdot \Delta}\quad{V_{DAC} \cdot K_{VCO}}}{2{\pi \cdot D}\quad A\quad C_{res}}},}\end{matrix} & (20)\end{matrix}$If the frequency axis of the VCO characteristics is expressed in Hertzinstead of radians per second, this may be expressed as: $\begin{matrix}{K_{gain} = \frac{\Delta\quad{T \cdot \Delta}\quad f_{VCO}}{D\quad A\quad C_{res}}} & (21)\end{matrix}$

All the parameters from the above equations can easily be obtained fromthe supplier data sheets for the DAC and VCO. This enables the PLLsoftware to compute the gain constant K_(gain) of the PLL from availableinformation once initial components have been selected. With the rightchoice of these components, the only unknown component which is the loopfilter, G_(LF)(s), can then be designed to obtain the desired systemsteady-state behavior. Accordingly, these equations may be used in acomputer program to enable a second order PLL to be designed given a setof performance specifications, (e.g., system damping factor, etc.) andcomponent characteristics.

In a similar manner, as described below, a computer program may also beused to design a third-order PLL (that is, a PLL with a second-orderloop filter), which may be used to obtain improved performance over thetraditional second-order PLL (a PLL with a first-order loop filter).

The basic goal of a control system is meeting the performancespecifications for a given system. Performance specifications may beconsidered to be constraints put on the system response characteristics,and may be stated in any number of ways. Generally, performancespecifications take two forms: 1) frequency-domain specifications (i.e.,pertinent quantities expressed as functions of frequency), and 2)time-domain specifications (in terms of time response). The desiredsystem characteristics may be prescribed in either or both of the aboveforms. In general, they specify three important properties of dynamicsystems: 1) the speed of response, 2) the relative stability of thesystem, and 3) the system accuracy or allowable error.

A lag-lead filter (also known as a proportional-integral (PI) filter)has the following transfer function: $\begin{matrix}{{{G_{LF}(s)} = {\frac{\overset{\sim}{E}(s)}{E(s)} = {\frac{1 + {s\quad\tau_{2}}}{s\quad\tau_{1}} = {K_{1} + \frac{K_{2}}{s}}}}},} & (22)\end{matrix}$where τ₁ and τ₂ are time constants of the filter, K₁=τ₂/τ₁, and K₂=1/τ₁.The filter has a pole at s=0 and therefore behaves like an integrator.It has (at least theoretically) infinite gain at zero frequency. Theclosed-loop transfer function of the PLL if this type of filter is usedis: $\begin{matrix}{{G_{PLL}(s)} = {\frac{\Theta_{VCO}(s)}{\Theta_{ref}(s)} = \frac{K_{PD}K_{VCO}{G_{LF}(s)}}{s + {K_{PD}K_{VCO}{G_{LF}(s)}}}}} & (23) \\{{G_{PLL}(s)} = \frac{\frac{K_{gain}}{\tau_{1}}\left( {{\tau_{2}s} + 1} \right)}{s^{2} + {\frac{\tau_{2}K_{gain}}{\tau_{1}}s} + \frac{K_{gain}}{\tau_{1}}}} & (24)\end{matrix}$which is of the form: $\begin{matrix}{{{G_{PLL}(s)} = \frac{{2{\zeta\omega}_{n}s} + \omega_{n}^{2}}{s^{2} + {2{\zeta\omega}_{n}s} + \omega_{n}^{2}}},} & (25)\end{matrix}$where ω_(n) and ζ are the natural frequency and damping factors,respectively, and are specified in terms of K_(gain), τ₁ and τ₂ as:$\begin{matrix}{{\omega_{n} = \sqrt{\frac{K_{gain}}{\tau_{1}}}},} & (26) \\{\zeta = {\frac{\omega_{n}\tau_{2}}{2}.}} & (27)\end{matrix}$These two parameters are usually used to specify the performancerequirements of a system. The poles of the closed loop system ares _(0,1)=−ζω_(n) ±jω _(n)√{square root over (1−ζ²)}.   (28)

The damping factor has an important influence on the dynamics of a PLL.When ζ>1,the poles are real; and when ζ<1,the poles are complex andconjugate. When ζ=1, the poles are repeated and real and the conditionis called critical damping. When ζ<1, the response is underdamped andthe poles are complex.

The transient response of the closed-loop system is increasinglyoscillatory as the poles approach the imaginary axis when ζ approacheszero. The above model can be directly applied to the PLL in thecontinuous-time domain.

Another important piece of information to know about a given PLL is thesteady-state error, that is, the error remaining after all thetransients have died out. The equation for the error transfer functionis: $\begin{matrix}\begin{matrix}{{G_{e}(s)} = \frac{\Theta_{e}(s)}{\Theta_{ref}(s)}} \\{= \frac{{\Theta_{ref}(s)} - {\Theta_{VCO}(s)}}{\Theta_{ref}(s)}} \\{= \frac{s}{s + {K_{PD}K_{VCO}{G_{LF}(s)}}}} \\{{= {1 - {G_{PLL}(s)}}},}\end{matrix} & (29) \\{{G_{e}(s)} = {\frac{s^{2}}{s^{2} + {\frac{\tau_{2}K_{gain}}{\tau_{1}}s} + \frac{K_{gain}}{\tau_{1}}}.}} & (30)\end{matrix}$

To understand how a PLL will respond, the performance of the PLL todifferent disturbances occurring at t=0 may be examined. Knowing theerror transfer function G_(e)(z) of the PLL, it is possible to determinethe response on the important excitation signals such as phase step,frequency step and frequency ramp at the input. The idea here is toanalyze the steady-state errors after any transients have died away.These steady-state error is readily evaluated by means of the finalvalue theorem, which states that: $\begin{matrix}{{\lim\limits_{t->\infty}{\theta_{e}(t)}} = {{\lim\limits_{s->0}{s\quad{\Theta_{e}(s)}}} = {\lim\limits_{s->0}{s\quad{G_{e}(s)}{{\Theta_{ref}(s)}.}}}}} & (31)\end{matrix}$

To determine how a PLL will respond to a phase step applied at the PLLinput, it is possible to look at the steady-state error resulting from astep change of input phase of magnitude Δθ. At t=0, the following stepfunction is applied:θ_(ref)(t)=Δθ·u(t)   (32)where u(t) is the unit step function. In the s-domain, this can beexpressed as: $\begin{matrix}{{\Theta_{ref}(s)} = {\frac{\Delta\quad\theta}{s}.}} & (33)\end{matrix}$Application of the final value theorem to the phase error functionyields: $\begin{matrix}{{\lim\limits_{t->\infty}{\theta_{e}(t)}} = {{\lim\limits_{s->0}{s\quad{G_{e}(s)}\frac{\Delta\quad\theta}{s}}} = 0.}} & (34)\end{matrix}$The above shows there is no steady-state error resulting from a stepchange of phase. This shows that the loop will eventually track anychange of input phase.

Although the PLL will track a phase step, that is not the only type ofchange that may be applied to the PLL. For example, it is also necessaryto determine the behavior of the PLL if a phase ramp (i.e., frequencystep) is applied at the PLL input, for example a frequency step ofmagnitude Δω applied at the input. Because the phase θ_(ref)(t) is theintegral over the frequency:θ_(ref)(t)=Δω·t,   (35)which shows that the input phase is a ramp with slope Δω. In thes-domain this may be expressed as: $\begin{matrix}{{\Theta_{ref}(s)} = {\frac{\Delta\omega}{s^{2}}.}} & (36)\end{matrix}$Applying the final value theorem results in the following equation:$\begin{matrix}{{\lim\limits_{t->\infty}{\theta_{e}(t)}} = {{\lim\limits_{s->0}{s\quad{G_{e}(s)}\frac{\Delta\quad\omega}{s^{2}}}} = 0.}} & (37)\end{matrix}$which shows that the phase error tends to zero as t→∞.

Another type of perturbation that may occur is a frequency ramp appliedat the PLL input. To determine how this affects the PLL performance,assume that the frequency ramp has a magnitude of Δ{dot over (ω)}applied at the input. Because the phase θ_(ref)(t) is the integral overthe frequency it may be shown that: $\begin{matrix}{{{\theta_{ref}(t)} = {\Delta{\overset{.}{\omega} \cdot \frac{t^{2}}{2}}}},} & (38)\end{matrix}$where the input frequency is a ramp with slope Δ{dot over (ω)}. In thes-domain this may be expressed as: $\begin{matrix}{{\Theta_{ref}(s)} = {\frac{\Delta\overset{.}{\omega}}{s^{3}}.}} & (39)\end{matrix}$Applying the final value theorem, it may be shown that: $\begin{matrix}{{\lim\limits_{t->\infty}{\theta_{e}(t)}} = {{\lim\limits_{s->0}{s\quad{G_{e}(s)}\frac{\Delta\quad\overset{.}{\omega}}{s^{3}}}} = {\frac{\tau_{1}\Delta\overset{.}{\omega}}{K_{gain}} = {\frac{\Delta\overset{.}{\omega}}{\omega_{n}^{2}}.}}}} & (40)\end{matrix}$For Δ{dot over (ω)}=1,${\underset{t->\infty}{\lim\quad}{\theta_{e}(t)}} = {\tau_{1}/{K_{gain}.}}$This show that the phase error tends to zero as t→0 only for high-gainloop. For a low-gain loop, the PLL would exhibit a non-zero steady-statephase error in the presence of a frequency ramp.

These equations may be used, for example in a computer program product,to design a loop filter for a PLL. A number of parameters of the designhave to be specified before applying the following design steps. Theseparameters include, the center frequency of the VCO ω_(o), and dampingfactor ζ. Conventional programming techniques may be used to implementthe computer program given the equations set forth above, and theinvention is not limited to a particular implementation using aparticular computer language or operating system.

Apart from the VCO, all the other components in the PLL are digital. ThePLL may therefore be considered a digital PLL. In the PLL, the samplingof the phase error e(t) (and the computation of the filtered error{tilde over (e)}(t)) occurs every ΔT bits assuming a delay variationfree system. The period of ΔT bits is equivalent to a sampling period ofΔt=ΔT/f_(o), where f_(o) is the nominal system frequency in bits persecond. Through simulations and laboratory experiments, it has beenobserved that ΔT should be selected to be very high (e.g., ΔT≧308800bits for T1 rate) in order to minimize the loop tracking error (due tothermal noise, input phase dynamics, and in particular, network delayvariation).

To design a digital PLL, it is possible to use a known approach commonlyreferred to as design by emulation. The design by emulation approachinvolves designing a continuous time loop filter, digitizing thecontinuous time loop filter, and then using discrete analysis,simulations, or experimentation to verify the design. Design byemulation yields good results only when the sampling ratesω_(samp)=2π/Δt are at least 20ω_(n), that is ω_(n)Δt≦2π/20. In thefollowing example, the following value has been selected ω_(n)Δt=2π/35.

To design a second order loop, the first step is to collect the designpre-specifications. Specifically, the center frequency of the VCOω_(o)=2πf_(o) will be specified at this stage of the design process.This parameter is usually obtained from the VCO data sheet that isprovided by the VCO supplier. Additionally, the damping factor ζ shouldbe specified. These values may be input (200) to the PLL design computerprogram for use by the program in connection with designing the PLL.

The gain of the DAC will then need to be computed. If the DAC registeris specified as L bits long, giving the DAC a resolution ofDAC_(res)=2^(L), then the gain K_(gain) may be computed using thefollowing equation$K_{gain} = {\frac{\Delta\quad{T \cdot \Delta}\quad{V_{DAC} \cdot K_{VCO}}}{2{\pi \cdot 2^{L}}}.}$To enable the PLL design software to compute the gain, the length L ofthe DAC should be input to the PLL design software.

Once the gain is determined, the natural frequency ω_(n) of the PLL willbe determined by the PLL design software using the following equation:$\begin{matrix}{\omega_{n} = \frac{2\pi}{35\quad\Delta\quad t}} & (41)\end{matrix}$

The PLL design software will then determine the parameters τ₁ and τ₂ ofthe loop filter from the following two equations: $\begin{matrix}{\tau_{1} = \frac{K_{gain}}{\omega_{n}^{2}}} & (42) \\{\tau_{2} = \frac{2\zeta}{\omega_{n}}} & (43)\end{matrix}$Knowing the natural frequency, it is possible to also determine thelock-in time T_(L) (also called the setting time) as $\begin{matrix}{T_{L} \approx {\frac{2\pi}{\omega_{n}}.}} & (44)\end{matrix}$

Once these parameters have been calculated, the PLL design software willproceed to determine the stability characteristics of the PLL. Knowingwhether a system is absolutely stable or not is generally insufficientinformation for most control applications. Specifically, even if asystem is stable, it is often desirable to know how close it is to beingunstable. To do this, the PLL design software will need to be able tocalculate the relative stability of the system. In addition toexplaining how the relative stability may be determined, the followingdiscussion will also help explain how the PLL design software may beused to design a third-order PLL.

The open-loop transfer function of the PLL will be denoted as:K_(OL)G_(OL)(s)=G_(PD)(s)G_(LF)(s)G_(DAC)(s)G_(VCO)(s). From this, it ispossible to define the following two important measures that are used toindicate the stability margin in a system:

-   -   The gain margin (GM), which is a measure of relative stability,        is defined as the magnitude of the reciprocal of the open-loop        transfer function, evaluated at the frequency ω_(c) at which the        phase angle is −180°. This is, $\begin{matrix}        {{{GM} \equiv \frac{1}{{K_{OL}{G_{OL}\left( {j\omega}_{c} \right)}}}},} & (45)        \end{matrix}$    -   where argK_(OL)G_(OL)(jω_(c))=−180°=−π radians and ω_(c) is        called the phase crossover frequency. The gain margin of the        system is the factor by which the gain K_(OL) can be raised        before instability results. |GM|<1 (or |GM|<0 dB) indicates an        unstable system.    -   The phase margin (PM), φ, which is a measure of relative        stability, is defined as 180° plus the phase angle φ₁ of the        open-loop transfer function at unity gain. That is,        φ≡[180+argK_(OL)G_(OL)(jω₁)] degrees,   (46)    -   where |K_(OL)G_(OL)(jω₁)|=1 and ω₁ is called the gain crossover        frequency. The phase margin is the amount by which the phase of        G_(OL)(jω) exceeds −180° when |K_(OL)G_(OL)(jω)|=1. A positive        phase margin is required for stability.

In a typical case, the gain margin can be read directly from the Bodeplot by measuring the vertical distance between the |K_(OL)G_(OL)(jω)|curve and the |K_(OL)G_(OL)(jω)|=1 line at the frequency where∠K_(OL)G_(OL)(jω)=180°. The gain margin can also be determined from theroot locus with respect to K_(OL) by noting two values of K_(OL): at thepoint where the locus crosses the jω-axis, and at the nominalclosed-loop poles. The GM is the ratio of these two values.

Both unity gain and 180° excess phase shift (i.e., more negative thanthe −180° that is built in with negative feedback) are necessary foroscillations so the margins relative to this pair of conditions become ameasure of stability. Gain margin is the additional gain necessary togive unity open-loop gain when the open-loop excess phase is 180°. Phasemargin is the additional open-loop phase shift necessary to give 180°excess phase when the open-loop gain is unity. All PLLs have −90° phaseshift due to the 1/s term, so excess phase is 90° even before any effectfrom the loop filter is considered. Whether a loop will oscillate whenits gain exceeds unity at 180° is more easily seen from the Nyquist plotor from the root locus plot than from the Bode plot. However, in mostcases it will not operate properly under these conditions, and the Bodeplot is adequate.

As set forth above, the PLL design software may use this process todesign a second-order PLL. However, as shown in FIGS. 12 a and 12 b, thecharacteristics of a third-order PLL may be more advantageous than thoseof a second-order PLL. Accordingly, in certain circumstances it may beadvantageous to design a third-order PLL.

Although mathematically more tedious to analyze, it has been shown thatthe type 2 third-order loop has better noise suppression and fasterlockup time. As used herein, the order of the loop is defined as beingequal to the number of poles in the open-loop transfer function. This isalso the highest power of s in the denominator. The loop type is thenumber of such poles that are at the origin, s=0.

Compared to second-order loop PLL design, there are very fewpublications on third-order loops. This is partly because of thefar-greater popularity of the second-order loop, and also because of thegreater complexity involved in analyzing the third-order loops. Thetransfer function of the filter in a loop may be given as:$\begin{matrix}{{G_{LF}(s)} = {\frac{1}{1 + {s\quad\tau_{3}}}{\frac{1 + {s\quad\tau_{2}}}{s\quad\tau_{1}}.}}} & (47)\end{matrix}$With this filter, the loop has two perfect integrators, one being theVCO and one being the phase integrator part of the filter, and threetime constants.

The closed-loop transfer function of the third-order loop may beexpressed as: $\begin{matrix}\begin{matrix}{{G_{PLL}(s)} = \frac{K_{gain}{G_{LF}(s)}}{s + {K_{gain}{G_{LF}(s)}}}} \\{= \frac{K_{gain}\left( {{\tau_{2}s} + 1} \right)}{{\tau_{1}\tau_{3}s^{3}} + {\tau_{1}s^{2}} + {K_{gain}\tau_{2}s} + K_{gain}}} \\{= \frac{\frac{K_{gain}}{\tau_{1}\tau_{3}}\left( {{\tau_{2}s} + 1} \right)}{s^{3} + {\frac{1}{\tau_{3}}s^{2}} + {\frac{K_{gain}\tau_{2}}{\tau_{1}\tau_{3}}s} + \frac{K_{gain}}{\tau_{1}\tau_{3}}}}\end{matrix} & (48)\end{matrix}$Applying the final value theorem, it is possible to determine thesteady-state response of the loop to different input signals 1/s^(n),phase step (n=1), frequency step (n=2), frequency ramp (n=3), etc. Theerror transfer function for the third-order loop is given as:$\begin{matrix}{{G_{e}(s)} = {{1 - {G_{PLL}(s)}} = \frac{s^{3} + {\frac{1}{\tau_{3}}s^{2}}}{s^{3} + {\frac{1}{\tau_{3}}s^{2}} + {\frac{K_{gain}\tau_{2}}{\tau_{1}\tau_{3}}s} + \frac{K_{gain}}{\tau_{1}\tau_{3}}}}} & (49)\end{matrix}$So, by applying the final value theorem, when the loop is driven by1/s^(n), the error response approaches a final value of: $\begin{matrix}{{\underset{t->\infty}{\lim\quad}{\theta_{e}(t)}} = {{\underset{s->0}{\lim\quad}s\quad{G_{e}(s)}\frac{1}{s^{n}}} = {\underset{s->0}{\lim\quad}\frac{\tau_{1}}{K_{gain}}{s^{3 - n}.}}}} & (50)\end{matrix}$

This indicates that the phase error resulting from a phase step (n=1) ora frequency step (n=2) will settle to zero, and the phase error will notreach steady state for n>3. A frequency ramp (n=3)) will produce asteady-state phase error of${{\lim\limits_{t->\infty}\quad{\theta_{e}(t)}} = {\tau_{1}/K_{gain}}},$the same phase error that occurs in the second-order loop. This is notsurprising since one way to realize the third-order loop is to add alow-pass filter to the lag-lead filter (of the second-order loop above).The output of a low-pass filter driven by a ramp is another ramp withthe same slope, offset from the input by a constant.

Given a set of pre-specified design parameters φ (the phase margin) andω_(n) (the natural loop frequency), it is possible to obtain the designthe parameters τ₁, τ₂, and τ₃ of the third-order loop. Derivation ofthese parameters is known in the art, for example as taught by U. L.Rohde, Digital PLL Frequency Synthesizers: Theory and Design,Prentice-Hall, Englewood Cliffs, N.J., 1983, the content of which ishereby incorporated by reference. To get acceptable stability of theloop, a phase margin of at least 30° is generally required, although atypical design choice is 45°.

To design a third order loop, the PLL design software will first enablethe user to input the design pre-specifications. Specifically, the userwill be allowed to input the phase margin φ for the loop. As mentionedabove, a typical value for the phase margin is φ=45°. The PLL softwarewill also allow the user to specify the natural loop frequency, whichmay assume a value similar to that described above with respect to thesecond-order loop, ω_(n)=2π/35Δt. By selecting this parameter to be thesame as the second order loop described above, the bandwidth of thethird-order loop may be expected to be close to that of the second-orderloop.

Given these parameters, the PLL design software will compute thefollowing parameters τ₁, τ₂, and τ₃ as follows:

Compute the time constant τ₃ as follows: $\begin{matrix}{\tau_{3} = {\frac{{{- \tan}\quad\phi} + {{1/\cos}\quad\phi}}{\omega_{n}}.}} & (51)\end{matrix}$

Then compute the time constant τ₂ using: $\begin{matrix}{\tau_{2} = {\frac{1}{\omega_{n}^{2}\tau_{3}}.}} & (52)\end{matrix}$

Next, compute the last time constant τ₁ from: $\begin{matrix}{{\tau_{1} = {\frac{K_{gain}}{\omega_{n}^{2}}\sqrt{\frac{1 + {\omega_{n}^{2}\tau_{2}^{2}}}{1 + {\omega_{n}^{2}\tau_{3}^{2}}}}}},{K_{gain} = {\frac{\Delta\quad{T \cdot \Delta}\quad f_{VCO}}{{DAC}_{res}}.}}} & (53)\end{matrix}$

FIG. 12 shows the frequency response of second- and third-order PLLsthat may be designed using this process. These plots are obtained fromequations (24) and (48), respectively, for the second-order andthird-order loops. From these figures it can be seen that the delayvariation suppression characteristics of the third-order PLL are muchbetter than that of the second-order PLL. The parameters used in theplots are: ζ=0.707, DAC_(res)=2¹²=4096, f_(o)=1.544×10⁶ MHz,Δppm=0.0002, ΔV_(DAC) =1.5 Volts, Δf_(VCO)=308.8 Hz, ΔT=30880 bits(Δt=0.02 s), K_(gain)=2328.06, ω_(n)=8.97598 rad/s, second-order loop(τ₁=28.8956 s, τ₂=0.157532 s), third-order loop (φ=45°,τ₁=69.76 s,τ₂=0.268964 ms, τ₃=0.0461469 ms). The invention is not limited to thisparticular example, which was rather provided to illustrates theperformance differences between second and third order loops.

In the proceeding description, a software program that may implement aprocedure for designing the loop filters for the second- and third-orderloops has been described in the continuous-time domain. Once the PLL isdesigned using the PLL design software, the phase detector and loopfilter have to be implemented in digital form on a processor or inhardware form since the PLL using timestamps is a digital PLL. To dothis, the continuous-time representations of the loop filters may bedigitized. To do this design by emulation principles may be used wherebya continuous time filter is first designed and then digitized to obtaina discrete time filter. The digitization procedure in this instance maybe done using the Tustin's or bilinear approximation of thecontinuous-time functions.

For example, knowing the two parameters of the loop filter of the secondorder PLL, G_(LF)(s), it would be desirable to find a set of differenceequations (or G_(LF)(z) for the digital implementation of the filter).Using the Tustin's or bilinear approximation for the digitization ofG_(LF)(s), it is possible, for every occurrence of s in the loop filter,to substitute: $\begin{matrix}{{s = {\frac{2}{\Delta\quad t}\left( \frac{1 - z^{- 1}}{1 + z^{- 1}} \right)}},} & (54)\end{matrix}$where Δt is the sampling interval for the system. Accordingly:$\begin{matrix}{{{G_{LF}(z)} = {\left. {G_{LF}(s)} \right|_{s = {\frac{2}{\Delta\quad t}{(\frac{1 - z^{- 1}}{1 + z^{- 1}})}}} = {\frac{\overset{\sim}{E}(z)}{E(z)} = \frac{1 + {\frac{2\tau_{2}}{\Delta\quad t}\left( \frac{1 - z^{- 1}}{1 + z^{- 1}} \right)}}{\frac{2\tau_{1}}{\Delta\quad t}\left( \frac{1 - z^{- 1}}{1 + z^{- 1}} \right)}}}},} & (55)\end{matrix}$which gives the following difference equation for implementing the loopfilter for the second-order loop: $\begin{matrix}{{\overset{\sim}{e}(n)} = {{\overset{\sim}{e}\left( {n - 1} \right)} + {\frac{{\Delta\quad t} + {2\tau_{2}}}{2\tau_{1}}{e(n)}} + {\frac{{\Delta\quad t} - {2\tau_{2}}}{2\tau_{1}}{{e\left( {n - 1} \right)}.}}}} & (56)\end{matrix}$With this equation, the phase detector and the loop filter can beimplemented in the digital domain with a sampling interval Δt. Thus,once a PLL has been designed using the PLL design software, the PLL maybe implemented in digital circuitry in a straightforward manner usingknown techniques.

Similarly, knowing the three parameters of the loop filter of thethird-order PLL, G_(LF)(z) may be obtained as follows: $\begin{matrix}\begin{matrix}{{G_{LF}(z)} = \left. {G_{LF}(s)} \right|_{s = {\frac{2}{\Delta\quad t}{(\frac{1 - z^{- 1}}{1 + z^{- 1}})}}}} \\{= \frac{\overset{\sim}{E}(z)}{E(z)}} \\{= {\frac{1 + {\frac{2\tau_{2}}{\Delta\quad t}\left( \frac{1 - z^{- 1}}{1 + z^{- 1}} \right)}}{\frac{2\tau_{1}}{\Delta\quad t}{\left( \frac{1 - z^{- 1}}{1 + z^{- 1}} \right)\left\lbrack {1 + {\frac{2\tau_{3}}{\Delta\quad t}\left( \frac{1 - z^{- 1}}{1 + z^{- 1}} \right)}} \right\rbrack}}.}}\end{matrix} & (57)\end{matrix}$This gives the following difference equation for implementing the loopfilter for the third-order loop: $\begin{matrix}{{\overset{\sim}{e}(n)} = {{\frac{4\tau_{3}}{{\Delta\quad t} + {2\tau_{3}}}{\overset{\sim}{e}\left( {n - 1} \right)}} + {\frac{\left( {{\Delta\quad t} - {2\tau_{3}}} \right)}{{\Delta\quad t} + {2\tau_{3}}}{\overset{\sim}{e}\left( {n - 2} \right)}} + {\frac{\Delta\quad{t\left( {{\Delta\quad t} + {2\tau_{2}}} \right)}}{2{\tau_{1}\left( {{\Delta\quad t} + {2\tau_{3}}} \right)}}{e(n)}} + {\frac{2\left( {\Delta\quad t} \right)^{2}}{2{\tau_{1}\left( {{\Delta\quad t} + {2\tau_{3}}} \right)}}{e\left( {n - 1} \right)}} + {\frac{\Delta\quad{t\left( {{\Delta\quad t} - {2\tau_{2}}} \right)}}{2{\tau_{1}\left( {{\Delta\quad t} + {2\tau_{3}}} \right)}}{e\left( {n - 2} \right)}}}} & (58)\end{matrix}$These filter equations can be implemented in digital form in a processoror as a hardware computational component of the PLL. Accordingly, once athird-order PLL has been designed using the PLL design software, the PLLmay be implemented in hardware in a straightforward manner.

To determine the filtered Error-to-DAC/VCO mapping function, thefrequency resolution f_(res) of the VCO will be defined to be:$\begin{matrix}{f_{res} = {\frac{{f_{o} \cdot \Delta}\quad{ppm}}{{DAC}_{res}}.}} & (59)\end{matrix}$As shown below, a combined DAC-VCO model may be developed which can thenbe used to develop the error mapping function for the PLL. Specifically,assume that the DAC register is specified to be L bits long, giving theresolution of the DAC_(res)=2^(L). The error mapping function maps afiltered error value {tilde over (e)}, which is a floating point number,to a corresponding DAC input value, which is a integer in the range[0,2^(L)−1].

To develop a combined DAC-VCO model, the DAC input DAC_(VCO) (DAC_(VCO)ε [0,DAC_(res)−1]) will be defined as:DAC _(VCO)(t)=DAC _(o)+{tilde over (e)}(t)=DAC _(o) +DAC _(corr)(t)  (60)where DAC_(corr)(t)={tilde over (e)}(t) is the filtered error andDAC_(o) is the nominal DAC value (corresponding to the nominal frequencyf_(o)). The VCO output frequency can then be expressed as:$\begin{matrix}\begin{matrix}{{f_{VCO}(n)} = {f_{res}D\quad A\quad{C_{VCO}(t)}}} \\{= {f_{res}\left\lbrack {{D\quad A\quad C_{o}} + {D\quad A\quad{C_{corr}(t)}}} \right\rbrack}} \\{= {f_{o} + {f_{res}D\quad A\quad{C_{corr}(t)}}}}\end{matrix} & (61)\end{matrix}$The above expression corresponds to an angular frequency:ω_(VCO)(t)=ω_(o)+2πf _(res) DAC _(corr)(t)=ω_(o) +K _(DAC-VCO) DAC_(corr)(t)=ω_(o)+Δω(t),   (62)where $\begin{matrix}{K_{{DAC} - {VCO}} = \frac{2{\pi \cdot f_{o} \cdot \Delta}\quad{ppm}}{D\quad A\quad C_{res}}} & (63)\end{matrix}$is the combined DAC-VCO gain. By definition, the phase of the VCOθ_(VCO) is given by the integral over the frequency variationΔω(t)=ω_(VCO)(t)−ω_(norm) as: $\begin{matrix}{{{\theta_{VCO}(t)} = {{\int_{0}^{t}{{{\Delta\omega}(x)}{\mathbb{d}x}}} = {K_{{DAC} - {VCO}}{\int_{0}^{t}{D\quad A\quad{C_{corr}(x)}{\mathbb{d}x}}}}}},} & (64)\end{matrix}$which is consistent with the DAC and VCO models developed above.

To develop the error mapping function, it will be assumed that the timegeneration period is constant, i.e., ΔT. In the PLL being developed, theinput frequencies f_(s) and {circumflex over (f)}_(s) are essentiallydivided down to lower frequencies which will be denoted as f_(ΔT) andf_(ΔR), respectively. In steady-state (or the tracking phase) of thePLL, f_(s)≈{circumflex over (f)}_(s) (or similarly f_(ΔT)≈f_(ΔR)).Additionally, assuming a given timestamp generation period of ΔT (whichis equal to ΔR in a system without delay variations), there is thefollowing frequency relationship for a system without delay variations:{circumflex over (f)}_(s)=ΔT ·f_(ΔT).

Accordingly, this shows that measurement and control are carried out atthe clock frequency f_(ΔT)≈f_(ΔR) which is essentially the samplingfrequency for the receiver PLL. The errors e(n) from the phase detectorare generated at this frequency f_(ΔT)≈f_(ΔR), but, the receiveroscillator operates at the service frequency f_(s)≈{circumflex over(f)}_(s). Also, the loop parameters derived above are based on thesampling frequency f_(ΔT)≈f_(ΔR). Thus, the error values generated atthe lower frequency f_(ΔT)≈f_(ΔR) have to be scaled to appropriatevalues so that they can applied to the receiver oscillator whichoperates at the service frequency f_(s)≈{circumflex over (f)}_(s).

To enable the errors to be mapped, new mapping functions must be createdto map the filtered error values generated by the loop filter (whichoperates at the lower nominal frequency f_(ΔT)=f_(o)/ΔT) intoappropriate values for the controlling the oscillator (which operates atthe higher nominal frequency f_(o)).

With a slight change of notation, DAC_(VCO)(f_(ΔT),t) will be used todenote the VCO control input at time t computed based on systemparameters at the scaled-down frequency f_(ΔT)≈f_(ΔR). Also,DAC_(VCO)(f_(o),t) will be used to denote the VCO control input at timet computed based on system parameters at the nominal frequency f_(o).Accordingly: $\begin{matrix}\begin{matrix}{{{\hat{f}}_{s}(t)} = {f_{o} + {f_{res}D\quad A\quad{C_{VCO}\left( {f_{o},t} \right)}}}} \\{= {{\Delta\quad{T \cdot {f_{o}\left( {f_{\Delta\quad T}(t)} \right)}}} + {f_{res}D\quad A\quad{C_{VCO}\left( {f_{o},t} \right)}}}}\end{matrix} & (65)\end{matrix}$from which the following equations may be derived: $\begin{matrix}\begin{matrix}{{f_{\quad{\Delta\quad R}}(t)} = {f_{\quad{\Delta\quad T}}(t)}} \\{= \frac{{\hat{f}}_{s}(t)}{\Delta\quad T}} \\{= {{f_{o}\left( f_{\Delta\quad T} \right)} + {f_{res}\frac{D\quad A\quad{C_{VCO}\left( {f_{o},t} \right)}}{\Delta\quad T}}}}\end{matrix} & (66)\end{matrix}$And, accordingly: $\begin{matrix}{{{D\quad A\quad{C_{VCO}\left( {f_{\Delta\quad T},t} \right)}} = \frac{D\quad A\quad{C_{VCO}\left( {f_{o},t} \right)}}{\Delta\quad T}}{{or}\text{:}}} & (67) \\\begin{matrix}{{D\quad A\quad{C_{VCO}\left( {f_{o},t} \right)}} = {\Delta\quad{T \cdot D}\quad A\quad{C_{VCO}\left( {f_{\Delta\quad T},t} \right)}}} \\{{= {{D\quad A\quad{C_{o}\left( f_{o} \right)}} + {\overset{\sim}{e}\left( {f_{o},t} \right)}}},}\end{matrix} & (68)\end{matrix}$where DAC_(o)(f_(o)) is the nominal DAC value corresponding to thenominal frequency f_(o), and {tilde over (e)}(f_(o),t) is the filterederror at time t computed based system frequency f_(o).

As discussed above:DAC _(VCO)(f _(ΔT) ,t)=DAC _(o)(f _(ΔT))+{tilde over (e)}(f _(ΔT) ,t),  (69)and the DAC/VCO operations have been defined around the nominal DACvalue DAC_(o)(f_(o)) and frequency f_(o) as $\begin{matrix}\begin{matrix}{{D\quad A\quad{C_{VCO}\left( {f_{o},t} \right)}} = {\Delta\quad{T \cdot D}\quad A\quad{C_{VCO}\left( f_{\Delta\quad T} \right)}}} \\{= {{D\quad A\quad{C_{o}\left( f_{o} \right)}} + {D\quad A\quad{C_{corr}\left( {f_{o},t} \right)}}}}\end{matrix} & (70)\end{matrix}$where DAC_(corr)(f_(o),t) is the DAC correction factor corresponding tothe nominal frequency f_(o), at time t. But it is also possible todefine the DAC/VCO operations around the DAC value DAC_(o)(f_(ΔT)) andfrequency f_(ΔT) as: $\begin{matrix}\begin{matrix}{{D\quad A\quad{C_{VCO}\left( {f_{\Delta\quad T},t} \right)}} = \frac{D\quad A\quad{C_{VCO}\left( {f_{o},t} \right)}}{\Delta\quad T}} \\{= {{D\quad A\quad{C_{o}\left( f_{\Delta\quad T} \right)}} + {D\quad A\quad{C_{corr}\left( {f_{\Delta\quad T},t} \right)}}}}\end{matrix} & (71)\end{matrix}$where DAC_(corr)(f_(ΔT),t) is the DAC correction factor corresponding tothe scaled down nominal frequency f_(ΔT), at time t.

From the above equation it may be shown that: $\begin{matrix}\begin{matrix}{{D\quad A\quad{C_{VCO}\left( {f_{o},t} \right)}} = {\Delta\quad{T \cdot D}\quad A\quad{C_{VCO}\left( {f_{\Delta\quad T},t} \right)}}} \\{= {{\Delta\quad{T \cdot D}\quad A\quad{C_{o}\left( f_{\Delta\quad T} \right)}} + {\Delta\quad{T \cdot D}\quad A\quad{C_{corr}\left( {f_{\Delta\quad T},t} \right)}}}}\end{matrix} & (72)\end{matrix}$Comparing (70) and (72), we get $\begin{matrix}{{{D\quad A\quad{C_{o}\left( f_{o} \right)}} = {\Delta\quad{T \cdot D}\quad A\quad{C_{o}\left( f_{\Delta\quad T} \right)}}},{and}} & (73) \\\begin{matrix}{{D\quad A\quad{C_{corr}\left( {f_{o},t} \right)}} = {\Delta\quad{T \cdot D}\quad A\quad{C_{corr}\left( {f_{\Delta\quad T},t} \right)}}} \\{= {\Delta\quad{T \cdot {\overset{\sim}{e}\left( {f_{\Delta\quad T},t} \right)}}}}\end{matrix} & (74)\end{matrix}$The above equation shows that, although, a filtered error {tilde over(e)}(f_(ΔT),t) is obtained based on the filter gains computed from thesystem parameters and the scaled down nominal frequencyf_(ΔT)=f_(s)/ΔT), a corresponding error {tilde over (e)}(f_(o),t) (whichis based on the VCO nominal output f_(norm) as shown in FIG. 13) canreadily be obtained by multiplying by the mapping factor ΔT. Thisequation allows for two frequency domains to be used in the PLL designand at the same time obtain correct control inputs for proper systemoperation.

Since the DAC takes integer values in the range DAC_(VCO)(f_(o),t) ε[0,2^(L)−1], the error {tilde over (e)}(f_(o),t)=ΔT·{tilde over(e)}(f_(ΔT),t) must be rounded off to the nearest integer before beingadded to DAC_(o)(f_(o)), that is, the error mapping function may beobtained asDAC _(VCO)(f _(o) ,t)=DAC _(o)(f _(o))+Int[ΔT·{tilde over (e)}(f _(ΔT),t)].   (75)The above error mapping function is straightforward and very simple toimplement as illustrated in FIG. 13.

The DAC has a nominal value that affects the operating frequency of theoscillator. Ideally, the nominal DAC setting would produce a voltagethat always caused the oscillator to produce the desired nominalfrequency. During tracking of the reference frequency, any errorencountered produces a DAC offset that, when added to the nominal DACsetting, minimizes the error (negative feedback control). In practice,the nominal DAC setting has to be determined and may have to bereadjusted during operation to account for temperature changes and agingeffects. In other situations, it may not be possible to accuratelydetermine the exact nominal DAC value. Therefore, it would be desirableto have a technique that can adaptively determine the optimal nominalDAC setting to eliminate the need to have an accurate initial DACsetting before use and/or to eliminate the need to manually readjust thenominal DAC setting during operation. Another advantage of adaptivelydetermining the optimal nominal DAC setting is that it enables the DACoffset computed during operation to be as small as possible. When theDAC offset needed to minimize the error is obtained, the error begins toget smaller and in turn, reduces the DAC offset, causing the error togrow again. When a large DAC offset is needed, the cycle will be longand the correction will be less accurate than when the DAC offset issmall.

Although a number of variations and optimizations are possible, thebasic techniques to adaptively re-compute the optimal nominal DACsetting are shown in FIGS. 14 a and 14 b. Specifically, FIG. 14 a showsa dynamic mapping function using samples in non-overlapping windows, andFIG. 14 b shows the dynamic mapping function using samples inoverlapping windows. Since these figures are self-explanatory,additional description of these figures has been omitted.

FIG. 16 shows a process that may be implemented in the PLL designsoftware to enable a second or third order PLL to be designed.Initially, when the software starts (200) the software will prompt theuser to input component characteristics for an initial selected set ofcomponents (202). The user will also be prompted, at this stage, toinput design specifications of the PLL to be designed (204). Inputtingdesign specifications and selected components may occur simultaneouslyor in any desired order and the invention is not limited to theparticular sequence shown in FIG. 15.

Once the initial information has been entered, either manually by anuser or automatically by another piece of software, the PLL designsoftware will compute the time constants for a loop filter that would berequired to enable the PLL top meet the design specifications given theselected components (206). These time constants may then be used todetermine the PLL behavior characteristics, such as the stability of thesystem. (208). If the PLL behavior characteristics are satisfactory, thePLL design is complete (212). If not, the PLL design software may usethe values of the time constants to help the user select differentcomponents that are more likely to produce a PLL with desirable behaviorcharacteristics (214). For example, the PLL design software may indicatethat the DAC does not have high enough resolution, or that a differentVCO may work better given the desired PLL design specifications.

FIG. 16 shows a computer system that may be used to implement the PLLdesign software according to an embodiment of the invention. Thecomputer system may be a standard computer and the invention is notlimited to any particular type of computer system. In the embodimentshown in FIG. 16, the computer 300 is connected to a display 302 fordisplaying results and one or more user input devices 304. The userinput devices may be stand-alone devices such as a keyboard or mouse, ormay be integrated into the display, such as where the display is touchor light sensitive. The invention is not limited to the particular typesof display and user input devices to be used with the computer.

The computer includes a display interface 306 and an input interface 308to receive and transmit signals from the display and user input devices.The computer also includes a CPU 310 configured to implement controllogic 312 so that the computer may perform the calculations describedabove to enable PLL design software 314 stored in memory 316 to beexecuted on the computer 300. A computer generally has many additionalcomponents that are not shown in this figure, as would be known to aperson of ordinary skill in the art. The invention is not limited to theparticular implementation shown in FIG. 16, but rather may beimplemented on many differently configured computer platforms.

Once a PLL has been designed, it may be implemented using discretecomponents, integrated circuitry, or using a combination of hardware andcontrol logic implemented as a set of program instructions that arestored in a computer readable memory within the network element andexecuted on a microprocessor. However, it will be apparent to a skilledartisan that all logic described herein can be embodied using discretecomponents, integrated circuitry, programmable logic used in conjunctionwith a programmable logic device such as a Field Programmable Gate Array(FPGA) or microprocessor, or any other device including any combinationthereof. Programmable logic can be fixed temporarily or permanently in atangible medium such as a read-only memory chip, a computer memory, adisk, or other storage medium. Programmable logic can also be fixed in acomputer data signal embodied in a carrier wave, allowing theprogrammable logic to be transmitted over an interface such as acomputer bus or communication network. All such embodiments are intendedto fall within the scope of the present invention.

It should be understood that all functional statements made hereindescribing the functions to be performed by the methods of the inventionmay be performed by software programs implemented utilizing subroutinesand other programming techniques known to those of ordinary skill in theart. It also should be understood that various changes and modificationsof the embodiments shown in the drawings and described in thespecification may be made within the spirit and scope of the presentinvention. Accordingly, it is intended that all matter contained in theabove description and shown in the accompanying drawings be interpretedin an illustrative and not in a limiting sense. The invention is limitedonly as defined in the following claims and the equivalents thereto.

1. A computer implemented method of designing a timestamp-basedthird-order Phase Locked Loop (PLL) for clock synchronization in apacket network, the PLL including a loop filter, a Digital to AnalogConverter (DAC), and an oscillator, the method comprising the steps of:specifying a center frequency of the oscillator, a register length ofthe of the DAC, and a desired damping factor of the PLL; computing, again coefficient of the PLL and a natural frequency of the PLL; anddetermining from the gain coefficient and the natural frequency, a setof required time constants for the loop filter that will enable the PLLto have the specified damping factor.
 2. The method of claim 1, whereinthe PLL is designed in two frequency domains.
 3. The method of claim 2,wherein the first and second frequency domains are related via a mappingfactor.
 4. The method of claim 3, wherein the mapping factor is based ona nominal interval between receipt of timestamps.
 5. The method of claim1, wherein the PLL is configured to receive timestamps and use thetimestamps to synchronize with a master clock.
 6. The method of claim 5,wherein the PLL has a first frequency domain associated with thefrequency of the local oscillator, and a second frequency domainassociated with a nominal timestamp arrival frequency.
 7. The method ofclaim 6, wherein the first frequency domain is a control frequencydomain, wherein the second frequency domain is an error measurementfrequency domain, the method further comprising the step of accountingfor a difference in the first frequency domain and the second frequencydomain by using in part a magnitude of a nominal sampling interval. 8.The method of claim 7, wherein the magnitude of the nominal samplinginterval is based on an average timestamp arrival interval.
 9. Themethod of claim 1, further comprising the step of determining adaptivelyan optimal nominal DAC setting to enable a DAC offset computed duringoperation to be as small as possible.
 10. The computer implementedmethod of claim 1, further comprising determining, from the timeconstants, PLL performance characteristics.
 11. The computer implementedmethod of claim 10, wherein the PLL performance characteristics comprisePLL stability characteristics.
 12. A computer implemented method ofdesigning a third-order timestamp-based Phase Locked Loop (PLL) forclock synchronization in a packet network, the PLL including a loopfilter, a Digital to Analog Converter (DAC), and an oscillator, themethod comprising the steps of: specifying a center frequency of theoscillator, a register length of the of the DAC, and a desired dampingfactor of the PLL; specifying a phase margin for the PLL; computing, thegain coefficient of the PLL and a natural frequency of the PLL;determining a transfer function of the loop filter by: computing a firsttime constant of the loop filter from the phase margin and the naturalfrequency; computing a second time constant from the natural frequencyand the first time constant; and computing a third time constant fromthe gain, the natural frequency, and the first and second timeconstants; wherein the first, second, and third time constants arecomputed to enable the PLL to have the desired specified damping factor.13. The computer implemented method of claim 12, wherein the localoscillator is a voltage controlled oscillator.
 14. Computer softwareconfigured to aid in the design of a third-order PLL, said PLLcomprising a phase detector, a loop filter, a digital to analogconverter, and a local oscillator, the computer software comprising:control logic configured to enable component characteristics of aninitial selected set of components to be specified, said initialselected set of components comprising at least the phase detector, thedigital to analog converter, and the local oscillator; control logicconfigured to enable design specifications of the PLL to be specified,said design specifications comprising at least a desired damping factorof the PLL; control logic configured to compute time constants for theloop filter that would be required to enable the PLL to meet thespecified design specifications given the specified componentscharacteristics; and control logic configured to determine, from thetime constants, PLL behavior characteristics for a PLL constructed usinga loop filter having those time constants and the initial set ofcomponents.
 15. The computer software of claim 14, further comprisingcontrol logic configured to use values of the time constants to selectdifferent components for the PLL that are more likely to provide the PLLwith better behavior characteristics.
 16. The computer software of claim14, further comprising control logic configured to compute a gaincoefficient of the PLL and a natural frequency of the PLL.
 17. Thecomputer software of claim 16, wherein the control logic configured tocompute time constants is configured to compute a first time constant ofthe loop filter from the phase margin and the natural frequency of thePLL; compute a second time constant from the natural frequency and thefirst time constant; and compute a third time constant from the gain,the natural frequency, and the first and second time constants; whereinthe first, second, and third time constants are computed to enable thePLL to have the desired specified damping factor.
 18. The computersoftware of claim 14, wherein the PLL is configured to receivetimestamps and use the timestamps to synchronize with a master clock.19. The computer software of claim 18, wherein the PLL has a firstfrequency domain associated with the frequency of the local oscillator,and a second frequency domain associated with a nominal timestamparrival frequency.
 20. The computer software of claim 19, wherein thefirst frequency domain is a control frequency domain, wherein the secondfrequency domain is an error measurement frequency domain, the computersoftware further comprising control logic configured to account for adifference in the first frequency domain and the second frequency domainby using in part a magnitude of a nominal sampling interval.
 21. Thecomputer software of claim 14, further comprising control logicconfigured to determine adaptively an optimal nominal DAC setting whichenables a DAC offset computed during operation to be as small aspossible.